1. Technical Field
The present invention relates to an architecture of a reading voltage generator for a matrix of EEPROM non-volatile memory cells of a semiconductor device.
More in particular, the invention relates to an architecture of a reading voltage generator which comprises at least one array enabled by an access transistor, the array comprising in turn at least one reference cell associated with a relevant select transistor, these select and access transistors and this reference cell being realized on a semiconductor substrate with active areas covered by a gate oxide layer and comprising a floating gate realized by a first polysilicon layer, covered by a dielectric layer and by a second polysilicon layer.
The present invention also relates to a process for manufacturing a voltage generator for a matrix of non-volatile memory cells of a semiconductor device.
2. Description of the Related Art
As it is well known, nowadays applications requiring the use of data storage device are more and more widespread such as for example semiconductor devices with EEPROM non-volatile memory cells.
These devices, in fact, show the characteristic of having an extremely reduced current consume both during a modify operation, such as programming or erasing of the content of the memory cells, and during a reading operation.
Moreover, with these devices it is possible to simultaneously erase more cells in parallel, single word by single word, and to program single bit by single bit, i.e., single cell by single cell.
EEPROM memory devices are widely used for example in the realization of Smart Cards.
The continuous request for miniaturization of Smart Cards and thus of the memory devices therein contained has pushed the research towards greater and greater integration scales, with a reduction of the sizes of the components. On the other hand, this makes it more critical the control of the characteristics of these components, in particular of memory cells, with more and more serious difficulties in ensuring acceptable reliability performances for reduced size cells.
It is also known that non-volatile memory cells are usually integrated on a substrate of semiconductor material and ordered in rows and columns for the formation of a matrix of cells, where the element for the information storage, i.e., the single cell, is a MOS transistor of the floating gate type. The amount of charge contained in the floating gate defines the logic state or level of the single cell.
In EEPROM memories, this amount of charge is altered by exploiting a passage of charges thanks to the tunnel effect through a thin silicon oxide layer, so called tunnel oxide, which is interposed between the substrate of semiconductor material and the floating gate of the cell transistor.
Express reference will be now made to EEPROM memory cells which provide two self-aligned polysilicon levels. A memory cell of this type is for example schematically shown in FIGS. 1A and 1B, globally indicated with 1, respectively shown along two perpendicular directions indicated with X and Y. The memory cell 1 is formed above a silicon substrate 2 with an overlapped gate oxide layer 3 and comprises a floating gate 5 realized by a first polysilicon layer polyfg and having size equal to Lpolyfg along the direction Y, as well as a control gate 7, realized by a second polysilicon layer poly2, overlapped onto the floating gate 5 and insulated from this latter by means of a dielectric layer 6 so called interpoly having thickness equal to thckpolyfg. Below this polysilicon floating gate 5 a channel region is defined having size equal to Wpolyfg along the direction X.
The memory cell 1 also comprises at least one active area 8 separated by field oxide portions 9A, 9B.
As shown in particular in FIG. 1B, the floating gate 5 of each memory cell 1 is electrically insulated from the floating gate 5 of each adjacent cell by means of suitable openings 4 having width equal to holepolyfg along the direction X, these openings being realized in the first polysilicon layer polyfg with a mask. In this way the electric discontinuity between the floating gates 5 of these cells is ensured.
During the realization of the memory cells 1 the mask allows the removal of the first polysilicon layer polyfg and the definition of the openings 4 between the memory cells 1 with successive filling of these openings 4 by the second polysilicon layer poly2 which is deposited above the dielectric layer interpoly 6.
An architecture of a memory device of the EEPROM type comprises, associated with each memory cell 1, a relative select transistor realized in a similar way to the memory cell 1 itself.
Generally, such an architecture also provides an associated circuitry comprising transistors which, according to the different embodiments, can comprise a single or a double polysilicon layer with or without the interpoly dielectric layer.
In any way, this circuitry comprises a reading voltage generator of the memory cells, schematically shown in FIG. 2, which can comprise an array of reference cells, realized as the memory cells and suitable for generating a reading reference voltage Vcg which, applied to the gate of each memory cell 1 of the matrix, allows to discriminate the programmed state from the erased state of the memory cell 1 itself.
In particular, the reading reference voltage Vcg generated by the voltage generator is used to read the current flowing in each memory cell 1. In a conventional way as shown in FIG. 3, for each memory cell 1 a high logic state “1” and a low logic state “0” are associated with a predetermined drain current value Id so as to discriminate a programmed state from an erased state of this cell. As it is known, the response curve Id(Vcg) is function of a capacity Cpp which is formed in the memory cell under examination between the second polysilicon layer poly2 and the first polysilicon layer polyfg above it in a direction Z substantially perpendicular to the directions X and Y whose value is given by:Cppstd=∈oxLpolyfg(Wpolyfg+2*thpolyfg)/thONO  (1)
Lpolyfg being the length of the floating gate 5, Wpolyfg being the length of this floating gate 5 in correspondence with the channel region, in particular between two successive openings 4, thpolyfg being the thickness of the first polysilicon layer polyfg and thONO the thickness of the interpoly layer 6.
Then, with reference to FIG. 1B the value of the capacity Cpp given by the above reported formula (2) comprises a first term which depends on the coupling between the first polysilicon layer polyfg and the second polysilicon layer poly2, and a second term which depends on the coupling between the first polysilicon layer polyfg and the second polysilicon layer poly2, in the direction X where the second polysilicon layer poly2 enters in the openings 4 between two adjacent floating gates.
It is advantageous to realize the reference cells of the reading voltage generator in a similar way to the memory cells 1 for ensuring a same response curve of these reference cells at an equal drain current Id and then, in particular, to have a same progress of reading reference voltage Vcg generated.
In the case in which the reference cell shows a different value of the interpoly capacity with respect to that of the memory cell 1, such as for example that shown in the diagram of FIG. 4, a voltage-current curve V-I is obtained with a different slope with respect to the curves defined by the high “1” and low “0” logic state. In the case indicated in FIG. 4 there is in particular a greater slope for the curve V-I of the reference cell and thus a same reading reference voltage Vcg defines a reduced difference between the current Iref generated by the reference cell and the drain current Id of a memory cell 1 to be read, when this latter is in a low logic state “0”. All this generates the possibility of confusion in the definition of the logic states of the memory cell 1 as read through the reference cell. In particular high logic states could be read for current values which instead should define low logic states.
It is thus understood that the reference cells of the reading voltage generator, for discriminating in a correct way the state of the memory cells, must have a capacity Cpp to which a parallel voltage-current curve V-I corresponds substantially contained between the curves defined by the high logic state “1” and by the low logic state “0” of the memory cell 1, as shown in FIG. 3.
In particular, FIG. 3 shows a curve V-I of a reference cell in a virgin or original state, i.e., without any charge in the relative floating gate, suitable for allowing the discrimination between the two memory cell states 1: high and low. It is obvious that in the case of multilevel cells more curves will be necessary for identifying different logic states of the multilevel memory cell.
It is usual, at the end of the manufacturing process, to discharge the reference cells through exposure to ultraviolet rays to bring the cells themselves to the condition of “virgin” cells. This exposure allows to completely discharge the charges possibly present in the floating gates of these reference cells. Naturally, any time it is necessary to recover the “virgin” state of the cells it is necessary to expose the cells themselves to the ultraviolet rays for completely discharging the relative floating gates.
Unfortunately, the extremely reduced sizes nowadays reached by the cells at the end of the manufacturing process make the discharge operation by means of exposure to UV rays exacting and complex. Further, any time the “virgin” state or a desired biasing state of the reference cells of the voltage generator is to be recovered, it is necessary to resort to the exposure to UV rays.
A technical problem is that of devising an architecture of a reference voltage generator for the reading of memory cells able to periodically discharge the floating gates of the reference cells contained therein without the use of UV rays maintaining a structure substantially similar to the current structure and showing a simple architecture as well as reduced realization times, in this way overcoming the limits and drawbacks which still affecting the circuits realized according to the prior art.